1. The Field of the Invention
The present invention relates to methods of making a plug and metallization line structure in microelectronic devices. More particularly the present invention relates to methods of minimizing resistance in the interface between plugs or contacts and the metallization lines connected to them. The present invention is also particularly drawn to methods of minimizing electromigration due to minimized interface resistance and selected alloying. The present invention is also drawn to improving depth-of-focus restrictions in the process of connecting plugs or contacts to metallization lines.
2. The Relevant Technology
The process of forming contacts in semiconductors and the subsequent wiring of those contacts have several technical obstacles. These obstacles arise during fabrication and may be due to the use of differing materials. Some obstacles include depth-of-focus photolithographic problems, dissimilar metal-metal interface problems, electromigration problems, and irregular or large grain formation problems.
One technical obstacle is depth-of-focus photolithographic requirements in metallization line formation. Formation of metallization lines follows contact plug formation. During contact plug formation, a metallization line used to form the plug may have a non-planar and irregular surface above the contact hole where the plug is to be formed. The non-planarity of the metallization layer is due to the use of a portion of the metallization material that is needed to fill up the contact hole. Non-planarity, and the rough topography of the metallization layer, causes depth of focus problems in subsequent photolithography steps. These problems cause irregular metallization line widths that lead to unpredictable resistances along the metallization lines, as well as unreliable device speeds.
The problem of a rough surface can be ameliorated by reflow methods, but even with reflow, there remains an uneven surface topography.
Another technical obstacle is resistance in metal-to-metal interfaces between plug and metallization line. This obstacle arises when two disparate metals make up the plug and metallization line, respectively, or even when two metals of the same composition are poorly interfaced. The process of forming contacts in semiconductors and the subsequent wiring of those contacts to form a completed integrated circuit conventionally comprises two steps. The first step comprises forming titanium or tungsten plugs that are filled into contact holes by such methods as cold or hot deposition, cold-slow, or hot-fast force filling, or metal reflow into the contact holes, followed by an etchback that leaves only titanium or tungsten plugs isolated in the underlying silicon substrate. The second step comprises forming a metallization line over the plugs.
Electrical conduction at the titanium or tungsten interface with the metallization line can be poor in that a completely connected interface area is difficult to substantially achieve, particularly where dissimilar metals are involved. Because resistance in electrical conduction is a function of cross-sectional area through a conductive body, a less than completely connected interface between plug and metallization line causes a higher resistance than that contemplated by the design geometries of the plug-to-metallization line surface area interface. In addition to incomplete interfacial contact, filling contact holes with titanium or tungsten requires high temperatures and pressures that cause large or irregular grain structures to grow. These large or irregular grain structures resist flow and etchback and do not conduct current as well as fine-grained structures.
Still other technical obstacles are electromigration and metal creep. These involve the transport of metal atoms opposite the direction of electron flow in the lines, and can lead to failure of the lines.
Alxe2x80x94Cu electromigration in a structure with Alxe2x80x94Cu metallization lines and Ti or W plugs is well established. The phenomenon occurs because Cu diffusivity through Ti or W is much lower than through Al. Therefore the Cu is depleted from the area of the Ti or W plug by the current flow and not replaced, leading to failure at the interface between the Ti or W plug and the Alxe2x80x94Cu metallization lines.
Metal creep, on the other hand, occurs due to the differences in the thermal coefficients of expansion between metals, insulators, and silicon wafers. The differences in thermal coefficients of expansion can build up stress in the metallization lines, which can lead to migration of atoms in the metallization line to the various areas of high stress and strain. This migration of atoms forms voids or vacancies in the metallization line which can cause creep failure. Additional solutions which can control both the electromigration and metal creep problems are desirable.
Yet another technical obstacle involves large or irregular grain growth during the formation of metallization lines. Large or irregular grain growth can be caused by high processing temperatures, a high contact channel density in a dielectric substrate, and the interfaces between disparate metals. For example, where a wetting surface layer is placed upon a substrate to assist in metal flow, interaction between the wetting surface layer and the metallization material can result in large or irregular grain growth.
In the case of a titanium or titanium nitride wetting surface layer, an aluminum metallization layer can react with the wetting surface layer to cause titanium aluminide intermetallic combinations that have large grain cluster formations. Large grain structures adversely affect reflow capabilities and resist planarization. Such adverse effects prevent proper plug filling and the result is poor electrical conductivity and slower and less reliable devices.
The present invention is drawn to methods of making a semiconductor substrate having thereon plug or contact connections to metallization lines, which methods minimize electrical resistance, relieve depth-of-focus restrictions during patterning of the metallization lines, and resist electromigration and creep failure between the plug or contact and the metallization line. In the context of this document, the term xe2x80x9csemiconductor substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure including but not limited to the semiconductor substrates described above.
A first method of the present invention comprises patterning a contact hole within an insulation layer situated on a semiconductor substrate or equivalent. The contact hole can be for a via, interconnect, or bit line. A first metal layer is then formed upon the insulation layer. If necessary for complete filling of the contact hole, additional steps are carried out by such methods as reflow or pressure fill. The first metal layer is then planarized to isolate a plug of the first metal layer in the contact hole within the insulation layer. After isolating the plug in the contact hole, a second metal layer is formed upon the insulation layer over and on an exposed end of the isolated plug. The second metal layer may then be planarized to a preferred thickness so as to render the same with a photo-notching resistant surface that alleviates stringent depth-of-focus requirements in forming metallization lines. Finally, metallization lines are patterned out of the second metal layer. The first and second metal layers can be composed of either a substantially pure metal or an alloy thereof.
A second method of the present invention comprises patterning a contact hole within an insulation layer situated on a substrate assembly or equivalent. A single layer of metal is then formed upon the insulation layer. If necessary for complete filing of the contact hole, additional steps are carried out by such methods as reflow or pressure fill. The single layer of metal is then planarized above the insulation layer to a thickness that is preferred for metallization lines. Finally, the single layer of metal is patterned to create therefrom a unitary structure of both metallization lines and a plug isolated in the contact hole of within the insulation layer. The single layer of metal can be composed of either a substantially pure metal or an alloy thereof.
A third method of the present invention comprises the same processing steps for the first metal layer. Selection of alloys of the first and second metal layers is required in the third method in which a heat treatment, after formation of the second metal layer, causes preferred metal species diffusion between the two metal layers. The preferred diffusion causes a substantially uniform concentration gradient at the interface between the first and the second metal layers that minimizes resistance, creep failure, and electromigration. The heat treatment can either precede or follow planarization of each of the first and second metal layers.
As an optional series of steps for any of the foregoing three methods, the contact hole can be filled with a plug of conductive material other than aluminum. The conductive material of which the plug is formed preferably comprises, but is not limited to, tungsten. It is also preferred that, prior to depositing the tungsten or other conductive material, a liner layer of a refractory metal nitride is first deposited. The refractory metal is deposited in an atmosphere of nitride and is subsequently annealed to serve as a barrier to prevent diffusion and chemical attack of the chemistry used to deposit the tungsten or other conductive material. The metal nitride is typically annealed to form a metal silicide at an interface with an underlying silicon substrate and to improve barrier properties of the metal nitride. The plug material is then deposited as described for one of the foregoing methods.
These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.